`timescale 10ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:19:53 03/24/2010
// Design Name:   rab_internal
// Module Name:   F:/Tesis/FPGA/rab_internal_tb.v
// Project Name:  ISE_Scanner_Project
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: rab_internal
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module rab_internal_tb;

	// Inputs
	reg clock;
	reg scanstart_n;
	reg reset;

	// Outputs
	wire regtclk;
	wire tferclk;
	wire adcclk;
	
	reg clk, control1, control2;
	wire PS1, PS3;
	clock_generator clock_gen (
		.clock_in(clk), 
		.reset(reset), 
		.clock_PS1(PS1), 
		.clock_PS2(), 
		.clock_PS3(PS3), 
		.clock8(), 
		.clk16(), //we only use the 16Mhz clock in thsi test
		.clock50()
	);

	// Instantiate the Unit Under Test (UUT)
	rab_internal uut (
		.clock(PS1), 
		.scanstart_n(scanstart_n), 
		.reset(reset), 
		.regtclk(regtclk), 
		.tferclk(tferclk), 
		.adcclk(adcclk)
	);
	
	always #1 clk = ~clk;//50Mhz clock

	integer counter;
	
	always @(posedge PS3) begin
		counter = counter + 1;
		if(counter == 1105) counter = 0;
	end	
		

	reg even_odd;
	always @(counter) begin
		if(counter[0]) even_odd = 1'b1;
		else even_odd = 1'b0;
	end
	
	task scan_even;
	begin
		@(negedge even_odd) scanstart_n = 1'b0;
		@(posedge even_odd)  scanstart_n = 1'b1;	
	end
	endtask


	task scan_odd;
	begin
		@(posedge even_odd) scanstart_n = 1'b0;
		@(negedge even_odd)  scanstart_n = 1'b1;	
	end
	endtask

	always @(counter) begin
		if(counter == 0) scanstart_n = 1'b0;
		else scanstart_n = 1'b1;
		
		if( (16'd13 <= counter) && (counter < 16'd15) ) control1 = 1'b0;
		else control1 = 1'b1;
		
		if( (16'd14 <= counter) && (counter < 16'd16) ) control2 = 1'b0;	
		else control2 = 1'b1;	
		
	end
	
	initial begin
		// Initialize Inputs
		clk = 0;
		scanstart_n = 1'b1;
		reset = 1;
		counter = 0;

		// Wait 100 ns for global reset to finish
		#100;
		reset = 0;
		
		#1000000	
		//scan_odd;
		
		#1000000		
		//scan_odd;
		
		#10000 $stop();
        
		// Add stimulus here

	end
      
endmodule

